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TABLE OF CONTENTS

 

Abstract…………………………………………………………………………………………………….iii Dedication………………………………………………………………………………………………….iv Acknowledgements…………………………………………………………………………………………v Table of Contents………………………………………………………………… ………………………vi
Chapter 1 : Introduction ………………………………………………………………………………………………….. 1
1.1 Introduction to System On Chip ……………………………………………………………………………. 1
1.2 Emergence of Network On Chip (NOC) …………………………………………………………………… 1
1.3 Related Work …………………………………………………………………………………………………….. 2
1.4 Problems of NOC………………………………………………………………………………………………… 3
1.4.1 Topology …………………………………………………………………………………………………….. 3
1.4.2 Buffer Size…………………………………………………………………………………………………… 3
1.4.3 Channel Width …………………………………………………………………………………………….. 3
1.4.4 Routing ………………………………………………………………………………………………………. 4
1.5 Project Contribution …………………………………………………………………………………………… 4
1.6 Report Organization ……………………………………………………………………………………………. 5
Chapter 2 : Network On Chip ……………………………………………………………………………………………. 6
2.1 Introduction ………………………………………………………………………………………………………. 6
2.2 On – Chip System Interconnection Overview ………………………………………………………….. 7
2.2.1 Bus – Based System ……………………………………………………………………………………… 7
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2.2.2 The NOC – Based …………………………………………………………………………………………. 8
2.2.3 NOC Designs Issues ………………………………………………………………………………………. 9
Chapter 3 : OASIS Interconnection Network ………………………………………………………………….. 15
3.1 Introduction …………………………………………………………………………………………………….. 15
3.2 OASIS NoC Architecture …………………………………………………………………………………….. 15
3.2.1 Switching ………………………………………………………………………………………………….. 16
3.2.2 Routing …………………………………………………………………………………………………….. 21
3.2.3 Flow Control ……………………………………………………………………………………………… 24
Chapter 4 : OASIS With Run Time Monitoring System………………………………………………………… 26
4.1 Introduction …………………………………………………………………………………………………….. 26
4.2 Algorithm ………………………………………………………………………………………………………… 27
4.2.1 Routing …………………………………………………………………………………………………….. 27
4.2.2 Switching ………………………………………………………………………………………………….. 32
4.3 Architecture …………………………………………………………………………………………………….. 32
4.3.1 Algorithm Implementation in Hardware…………………………………………………………. 33
Chapter 5 : Hardware and Software Evaluation Results ……………………………………………………… 38
5.1 Hardware Complexity ……………………………………………………………………………………….. 38
5.1.1 Logic ………………………………………………………………………………………………………… 38
5.1.2 Power ………………………………………………………………………………………………………. 39
5.1.3 Speed ……………………………………………………………………………………………………….. 39
5.2 Functional Simulation ……………………………………………………………………………………….. 40
5.2.1 Algorithm Verification …………………………………………………………………………………. 40
5.2.2 Packet Delay ……………………………………………………………………………………………… 41

 

CHAPTER ONE

 

1.1 Introduction to System On Chip
Complex applications, using System On Chips (SoCs) can be implemented by integrating more cores since the number of cores increases rapidly. That is, the rapid development of cores technology allows complex circuits to be integrated into a single chip. This also means that the system’s complexity also increases; hence designers tend to keep up with the increased complexity by using larger reusable blocks in their system design. However, with these different processing elements used together to achieve powerful systems, connecting these cores together posses a great challenge. And as the number of these computational units/processing units increases and are integrated into one silicon chip, communication between them becomes a problem. A communication system that will support these cores must be designed. Bus – based communication, where bus access request of nodes or cores are serialized through central arbiters, is a simple solution to the communication problem. However, this simple approach presents numerous challenges like scalability problem, bus capacitance increases dramatically with increase bus length and more additional cores, performance penalties, inefficient power or energy as the number of cores increases.
1.2 Emergence of Network On Chip (NOC)
NoC is a concept of communication in System on Chips (SoCs) [6,]. This concept claims to eliminate the problems of the Bus – based communication highlighted above. Unlike Bus – based communication where communication is done through buses and dedicated point-to-point links, Network On Chip, NoC, a more general scheme is adapted, employing a grid of routing nodes spread out across the chip, connected by communication links. The NoC design paradigm is centred communication rather than computation [4]. Each node (or tile) in the on-chip network is composed of a Processing Element (PE) and a communication unit which is so called
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a Network Interface (NI) as shown in Fig 1 below. The communication between the pairs of nodes is organized by connecting a network of routers and switching packages among them. The traditional bus-based on-chip communication architectures, the NoC solution provides higher communication scalability, flexibility, predictability, and power efficiency.
Fig 1: Regular structure of NoC
1.3 Related Work
Despite the fact that the concept of NoC is a relatively new field, it has in recent times, receive a lot of attention from research community. This is because of it has great potential to solving the On – Chip communication problems. In [6], [19] different NoC topologies are proposed with regular mesh topology being the simplest to implement with most routing schemes. There have been many routing algorithms which are based on wormhole routing proposed for meshes in the literature [7], [8], [10], [15], [16], all aimed at improving the performance of the routing strategies Network on Chip. These routing algorithms can be generally classified into three categories, depending on the degree of adaptiveness provided by the algorithms. A non-adaptive routing algorithm is deterministic and routes a packet from the source to the destination along a unique, predetermined path. A minimal fully adaptive routing algorithm routes all packets through any shortest paths to the destinations. A partially adaptive routing algorithm allows multiple choices for routing packets via shortest paths; in this case, it does not allow all packets to use any shortest paths.
0, 3
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Processing Element or Core
Network Adapter (NI)
Network Link
Routing Node or Switch
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1.4 Problems of NOC
NoC is an area receiving enough attention from researchers [5,6,7,9,10,12]. However, much work needs to be done in other to achieve the desired implementation of the NoC in practical. The following few problems are briefly discussed.
1.4.1 Topology
The underlying topology greatly affects the network’s ability to efficiently disseminate information across the network. The routing strategies of the network depend deeply on the topology of the network [12]. Also, the network topology has great impact on the network latency, fault tolerance, throughput, area, power consumption and mapping the cores to the network nodes. The grid -like structures are considered the simplest compared to the complexity of custom topologies. Hence mesh topology is considered more than others [12]. Flexibility on the other hand is provided more by customised topology and are most suitable for application – specific NoCs [13]. Regular topologies waste area when the sizes/shapes of the cores vary [13]. Generally, designing the network to meet the requirements of highly communicating cores will result in under-utilization of other components and for average case may result in performance bottleneck [14].
1.4.2 Buffer Size
In NoC, the buffer size of an input channel of the router or switch affects the overall area of the NoC. This implies that there is need for overall reduction in the buffer use to minimize NoC implementation overhead. On the order hand, increasing the buffer size can reduce the network latency, most especially, when the traffic pattern cannot be predicted and changes.
1.4.3 Channel Width
The width of the network channels affects the bandwidth of the NoC’s network channel. Increased width reduces latency; however, area increases [14]. NoC’s main problem here is how to obtain minimum network latency and maximum network throughput subject to area and power consumption constraints.
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1.4.4 Routing
One of the major problems of Network on Chip (NoC) is the routing of packets among the nodes. Deciding which output port to send the next packet as it traverses from source to destination is the key problem here. It has receive much attention by researchers, however with little practical implementation. Routing greatly affects the network performance and power consumption. Complicated routing strategies result in larger design resulting area and performance trade-offs [15 – 16]. Two routing strategies are proposed, deterministic and adaptive. Performance requirement and implementation complexity are major consideration when selecting a routing strategy. Deterministic routing, though, requires less resources, and guarantee packet arrival in order, it cannot respond to dynamic network conditions like congestion. The adaptive provides better throughput and lower latency since alternate path can be taken in case of traffic congestion [16]. Every routing scheme (Deterministic or Adaptive) has a primary goal of ensuring that every packet injected into the network will arrive its destination eventually. In NoC routing, packets may be involved in
 Livelock: Packets makes an infinite link traversal without reaching its destination as the time tends to infinity.
 Deadlock: This means that at a particular time, packets cannot advance or move further regardless of any policy applied throughout the network. There exists a circular dependency between different packets, in such a way that each packet is holding on to its own resources, on the other hand, it is trying to reserve resources which are being held by other packets
1.5 Thesis Contribution
This work focuses on the routing scheme implementation and the communication infrastructure of the OASIS Network on Chip. The contribution can be seen in two folds as follows: a). Routing algorithm Implementation in OASIS NoC. b). OASIS Run time Monitoring System. a. Routing Algorithm Implementation in OASIS NoC.
Existing OASIS NoC uses deterministic routing strategy to route packets from one node to another. That is, the X – Y coordinate static offline movement with no consideration to the network traffic. We implement adaptive routing scheme using the Odd/Even turn model. The scheme uses the input from the monitoring system about the traffic of the neighbouring nodes to adaptively route a packets.
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b. OASIS Run – Time Monitoring System We propose a run – time monitoring system that monitors the traffic of the whole network. Each router’s buffer size is monitored to provide the routers with
 Traffic information of its neighbours
 In case of high or low traffic in a particular switch, the monitoring system dynamically changes the buffer parameters to accommodate the traffic condition and reduce the overhead cause by increase or reduced buffer size.
1.6 Report Organization
This work will give an introduction to Network on Chip Design in Chapter 2. In this chapter, we will look at the system design problems, the interconnection that exist in the NoC, looking briefly at the bus – based and NoC based interconnection. Chapter 3 will introduce OASIS NoC interconnection where the OASIS architecture is discussed. Looking at its Switch or router architecture, the routing that existed with it flow control. Chapter 4 will discuss the OASIS NoC with run – time monitoring system, the algorithm and the architecture of the system. In Chapter 5, we will look at some hardware evaluation results like the power, speed etc of the OASIS. The chapter will also contain software evaluation of the system with some test bench to find the latency of the system. Chapter 6 will conclude the work with the necessary recommendations.

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