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ABSTRACT

Basically electrocardiography is a commonly used, non-invasive procedure for recording electrical
changes in the heart. The record, which is called an electrocardiogram (ECG or EKG), shows the series of
waves that relate to the electrical impulses which occur during each beat of the heart. The results are
printed on paper or displayed on a monitor. The waves in a normal record are named P, Q, R, S, T, U and
follow in alphabetical order. This research exploits the technology of parallel processing to process the
electrocardiography computational kernels in parallel. The idea we are presenting is to implement the
traditional multi lead bulky electrocardiogram on a programmable chip which is small and more efficient.
The technology is implemented on an FPGA (Target device is Altera Stratix III EP3SL50F484C2)
based on Multicore System on Chip. The Logic Utilization for one-lead system which is scalable to multi
lead after compilation was 43%, combinational ALUTs 9669/38000 (25%), Memory ALUTs 16/19000
(<1%), Total registers 11583/38000 (30%) and total thermal power dissipation of 463.86mW .

TABLE OF CONTENTS

Title Page ………………………………………………………………………………………………………………1
Abstract………………………………………………………………………………………………………………….2
Acknowledgement……………………………………………………………………………………………………3
Table of Contents…………………………………………………………………………………………………….7
List of Figures………………………………………………………………………………………………………….8
List of Tables……………………………………………………………………………………………………………9
Chapter One: Introduction……………………………………………………………………………………..10
1.0 Introduction……………………………………………………………………………………………10
1.1 Purpose of the research work…………………………………………………………………….11
1.2 Background…………………………………………………………………………………………….11
1.3 Scope of work………………………………………………………………………………………….12.
Chapter Two: Literature review………………………………………………………………………………13
2.0 Electrocardiography and heart disease………………………………………………………..13
2.1 Digital signal processing……………………………………………………………………………17
2.1.1 Analog and digital signals…………………………………………………………….17
2.1.2 Signal processing…………………………………………………………………………18
2.1.3 Analog to digital conversion………………………………………………………….18
2.1.4 Sampling……………………………………………………………………………………..19
2.1.5 Quantization error………………………………………………………………………..20
2.1.6 Sampling rate………………………………………………………………………………20
2.1.7 Oversampling………………………………………………………………………………21
2.1.8 Aliasing………………………………………………………………………………………21
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2.1.9 ADC structures……………………………………………………………………………22
2.1.10 Autocorrelation function……………………………………………………………..27
2.2 Digital filters………………………………………………………………………………………..28
2.2.1 Analysis techniques………………………………………………………………….29
2.2.2 Impulse response……………………………………………………………………..30
2.2.3 Difference equation………………………………………………………………….30
2.2.4 Filter design……………………………………………………………………………31
2.2.5 Filter realization………………………………………………………………………33
2.2.5.1 Direct form I………………………………………………………………………..34
2.2.5.2 Direct form II………………………………………………………………………34
2.3 Programmable Logic Devices………………………………………………………………..35
2.3.1 Programmable Array Logic (PAL)…………………………………………….37
2.3.2 Programmable Logic Array (PLA)…………………………………………….37
2.3.3 Generic Array Logic (GAL)……………………………………………………..38
2.3.4 Complex Programmable Logic devices (CPLD)………………………….39
2.4 Field Programmable Gate Array (FPGA)…………………………………………………40
2.4.1 History of FPGA……………………………………………………………………..41
2.4.2 Modern development……………………………………………………………….42
2.4.3 Architecture…………………………………………………………………………….43
2.4.4 FPGA design and programming…………………………………………………45
2.5 Multicore system on chip………………………………………………………………………46
2.5.1 Structure………………………………………………………………………………..47
2.5.2 Design flow……………………………………………………………………………47
2.6 Electronic design automation (EDA) tools………………………………………………49
2.6.1 System on programmable chip (SOPC) builder…………………………..50
2.6.2 Nios II processor……………………………………………………………………..50
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2.6.3 Hardware description Language (HDL)……………………………………..51
Chapter three: Analysis and Design…………………………………………………………………………..53
3.0 Peak period detection algorithm…………………………………………………………………..53
3.1 Period detection………………………………………………………………………………………..53
3.1.1 Reading data………………………………………………………………………………..54
3.1.2 Derivation……………………………………………………………………………………55
3.1.3 Autocorrelation…………………………………………………………………………….60
3.1.4 Finding intervals…………………………………………………………………………..70
3.2 Digital finite impulse response filter design FIR……………………………………………70
3.3 System architecture…………………………………………………………………………………….71
3.3.1 Reading data section……………………………………………………………………..72
3.3.2 Filtering and data analysis section…………………………………………………..73
3.3.3 Display section……………………………………………………………………………..74
Chapter four : Implementation and results………………………………………………………………..75
4.0 SOPC builder system generation and quartus II compilation……………………………75
4.1 Quartus II compilation of the entire design……………………………………………………76
4.2 Nios II IDE implementation of ppd algorithm………………………………………………..77
4.3 Results………………………………………………………………………………………………………79
4.3.1 Flow Summary………………………………………………………………………………79
4.3.2 Analysis and synthesis resources usage summary……………………………….80
4.3.3 Power analysis summary………………………………………………………………….81
4.3.4 Register transfer logic RTL of design………………………………………………..82
Chapter five : Conclusion and Future work………………………………………………………………..84
5.0 Conclusion…………………………………………………………………………………………………..84
5.1 Future work…………………………………………………………………………………………………84
References…………………………………………………………………………………………………………86

CHAPTER ONE

INTRODUCTION
1.0 INTRODUCTION
Technology over the years has been a tool that man has employed to make life a better place for
habitation. The importance of health to life cannot be over emphasised as it is a common saying that
health is wealth. In general our state of health is reflected in our heart beats, blood pressure, body
temperature and a whole lot of other parameters. The state of the heart is obviously the most important
since it is the power house of a man’s life. This research intend to develop a system that will monitor the
state of health of a person by analysing input signals from the body system of a person and sending the
result to a doctor in a remote location who will examine the analysed body signals and know the state of
health of the person in real time. It is a very interesting novelty. You don’t have to move here and there to
be examined by your doctor. It is a just in time and on the fly medical examination. In Africa and other
parts of the world there are some sick or elderly people who have mobility impedance. Such a class of
people need not border about mobility as the technology is all about best comfort. Again apart from sick
and elderly people every living soul needs this technology. The state of our heart is very important and a
lot of people just don’t care about the state of their hearts. Its not that they don’t want to but considering
the stress of going to the hospital, waiting for a doctor and paying for medical examination people are not
motivated to go for heart check up. With the technology being proposed heart medicine will experience a
great revolution as the boundaries of engineering are pushed beyond the limit. The technology will be
implemented on an FPGA. At a very high level of abstraction the system will accept input signals from the
user (like the probes of an ECG) but in this case in-body and then pass the signal through an analog to
digital converter (ADC). The result from the ADC is then filtered by passing it through a filter. Then to
memory. The resulting output is fed to EGC analyser for analysis of the filtered signal to generate
appropriate waveforms that reflect the state of health of the heart of the patient. The ECG analyses is
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performed by the algorithms known as the peak period detection algorithm. The intention is that the result
is then displayed on screen and routed to a doctor in some remote location who will do the necessary
prescription, but in this report the hardware design and compilation is done using the quartus II CAD
(Computer aided design) tool with the included SOPC(System on programmable chip) builder and then
the software programming is done using the NIOS II eclipse IDE for programming the NIOS II soft
processors in the work. The completed design is not downloaded to a DSP FPGA instead the results of
compilation from the CAD tools are shown.
1.1 PURPOSE OF THE RESEARCH WORK
The purpose of this reseach work is to design and implement an electrocardiogram on chip using
multicore system on chip technology exploiting parallel processing technology in processing the ECG
computational kernel. The entire ECG system is implemented on a DSP FPGA chip thus drastically
reducing the size of the traditional bulky ECG and at the same time improving accuracy and efficiency.
This is a great novelty as the result of the research will greatly improve the ECG system and health of the
people expecially elderly people and in developing countries with special focus on Africa.
1.2 BACKGROUND
As the importance of heart medicine cannot be overemphasised there have been lots of research in
the field of electrocardiography. With the advancement in system on chip technologies there has been a
concerted research move to change the paradym od the traditional bulky ECG implementation to a
complete system on chip implementation. Research work have been on in MIT, havard code blue project,
and very importantly in the Adaptive Systems Laboratory School of Computer Science and Engineering,
The University of Aizu under the umbrella of the BANSMOM project. What we are aiming at in this
research is to bend the beam of such research towards an African terrain.

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