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ABSTRACT

Nowadays, shifts in Hardware and Software technologies have forced designers and users to look at micro-architecture that process instructions stream with high performance and low power consumption.
In Striving for such high performance, the Queue Processor has been designed with architecture which has the following features:
 Low power consumption
 Smaller code size
 Simple Hardware
 High Performance in terms of Speed
 High Instruction level parallelism
This research aims at comparing and evaluating these performance features of the Queue Processor architecture with the traditionally used RISC architecture. Evaluation will be done in terms of Software (code size, execution time) and Hardware (Logical Elements, power and speed). This evaluation is performed using Quartus II IDE by Altera.
The QSoC will be used as case study for the Queue Processor while Aquarius will be used as case study for the RISC processor.
I’m confident that this evaluation research will show a significant improvement in the performance of the Queue Processor over the RISC Architecture.

TABLE OF CONTENTS

CHAPTER 1 – INTRODUCTION ……………………………………………………………………………………1
1.1 Importance of Performance Evaluation …………………………………………………………………….1
1.2 Research Objectives……………………………………………………………………………..2
1.3 Motivation of Research……………………………………………………………………2
1.4 Queue Computing…………………………………………………………………………3
1.5 Thesis Outline……………………………………………………………………………..4
CHAPTER 2 –LITERATURE REVIEW …………………………………………………………………………5
2.1 A Short History of Processor Architecture ………………………………………………………………..5
2.2 Measuring Processor Performance………………………………………………………..6
2.3 Conventional Processor……………………………………………………………………7
2.3.1 Issues with Conventional Processors…………………………………………………………………….7
2.3.2 Architectural Techniques……………………………………………………………….7
2.4 Produced Order Queue Computing………………………………………………………..9
2.5 Queue Core Architecture…………………………………………………………………13
2.5.1 ALU (Arithmetic Logic Unit)……………………………………………………..…..13
2.5.2 MLT (Multiplier, Divider and MOD Instructions)……………………………………14
2.5.3 LOAD/STORE………………………………………………………………………..14
2.5.4 SET……………………………………………………………………………………15
2.5.5 Branch…………………………………………………………………………………15
2.6 Instruction Pipeline Structure……………………………………………………………16
CHAPTER 3 – QUEUE Vs RISC MACHINES………………………………………………23
3.1 Queue Machine Analysis…………………………………………………………………24
3.1.1 Higher Instruction Level Parallelism (ILP)…………………………………………..24
3.1.2 Reduced Instruction Width……………………………………………………………26
3.1.3 Free from False Dependencies………………………………………………………..27
3.1.3.1 Register Renaming……………………………………………………………….27
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3.1.4 Drawbacks of Queue Machines…………………………………………………………29
3.2 QSoC Simulation and Synthesis…………………………………………………………30
3.3 Quartus II Overview……………………………………………………………………..30
3.4 FPGA Implementation of QSoC…………………………………………………………31
3.5 Pictorial Summary of Queue Machines Vs RISC Machines…………………………….32
CHAPTER 4 – COMPLEXITY ANALYSIS…………………………………………………34
4.1 Code Size…………………………………………………………………………………34
4.2 Synthesis Result (Logical Elements)…………………………………………………….36
4.3 Power and Speed Comparison Results…………………………………………………..37
CHAPTER 5 DICUSSION OF RESULTS…………………………………………………….39
CHAPTER 6 CONCLUSION………………………………………………………………….40
6.1 Future Work………………………………………………………………………………40
REFERENCES …………………………………………………………………………………41
APPENDICES
Appendix A Verilog Codes…………………………………………………………………..42
Top Level Module (QP_top.v)……………………………………………………………42
Memory Unit (QP_MU)…………………………………………………………………46
Queue Computation Unit (QP_QCU)……………………………………………………48
Writeback Unit (QP_WBU)………………………………………………………………53
Execution Unit (QP_EU)…………………………………………………………………55
Appendix B Screenshots……………………………………………………………………..67

CHAPTER ONE

INTRODUCTION
1.1 Importance of Performance Evaluation
Performance evaluation is at the foundation of computer architecture research and development. Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only.
Adequate performance evaluation methods are absolutely crucial to steer the research and development process in the right direction. However, rigorous performance evaluation is non-trivial as there are multiple aspects to performance evaluation, such as picking workloads, selecting an appropriate modelling or simulation approach, running the model and interpreting the results using meaningful metrics. Each of these aspects is equally important and a performance evaluation method that lacks rigor in any of these crucial aspects may lead to inaccurate performance data and may drive research and development in a wrong direction [04].
The major aims of Performance Evaluation are to:
 Collect and disseminate information relative to performance aspects, and in particular to a specific topic.
 Promote interdisciplinary flow of technical information among researchers and professionals.
 Serve as a publication medium for various special interest groups in the performance community at large.
1.2 Research Objectives
This research studies extensively, the Queue Processor Architecture in general and evaluates the QSoC (Queue System on Chip) in specific.
This research compares two different processor architectures: Queue Processor (using QSoC from ASL as case study) and RISC Processor (using Aquarius from OpenCores as case study).
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Through extensive simulation experiments, the performance of the Queue Processor is evaluated alongside the RISC Architecture.
This evaluation is done in terms of Hardware:
 Logical elements
 power
 speed
And Software:
 Code size
 Execution time
The work consists of three parts: initial analysis, implementation and benchmarking.
During the initial analysis, the processor architectures will be analyzed and compared based on characteristics such as pipeline depth, Instruction Set Architecture, data path and control path.
Each processor is synthesized and implemented on a DE-II FPGA board.
Characteristics such as gate count, maximum clock frequency, and performance is measured. Performance of the implemented processors is measured with a set of standard benchmarks.
This research is aimed at identifying the significant improvement in the performance of the Queue Processor over the RISC Architecture.
1.3 Motivation for Research
Nowadays, shifts in Hardware and Software technologies have forced designers and users to look at micro-architecture that process instructions stream with high performance and low power consumption.
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Queue computing and architecture design approaches take into account performance and power consumption considerations early in the design cycle and maintain a power-centric focus across all levels of design abstraction.
This is especially useful since power has become a problem in most countries. The importance of the use of a processor which consumes and dissipates less power cannot be over emphasized.
To address this issue, and especially to increase processing speed, it is believed that the Queue processor provides an interesting alternative to the design of embedded systems.
1.4 Queue Computing
The accelerated demand in increasing performance has resulted in the research into and the development of higher performance and less power consuming architectures which employ queue computing.
Queue Computing is simply processing data using queues. The queue data structure uses the FIFO (First In First Out) scheme whereby data that comes in first is processed first.
Queue computing model refers to the evaluation of expression using FIFO queue, called operand queue instead of registers as intermediate storage of results [02].
This model establishes two rules for the insertion and removal of elements from the operand queue. Operands are inserted, or en-queued, at the rear of the queue. And operands are removed, or de-queued, from the head of the queue. Two references are needed to track the location of the head and the rear of the queue. The Queue Head (QH) points to the head of the queue, and Queue Tail (QT) points to the rear of the queue [02].
Queue processors offer a very attractive alternative for the design of embedded processors given their characteristics of
 Small Instructions
 Simple Hardware
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 High Instruction Level Parallelism
 Free from False Dependencies
1.5 Thesis Outline
This thesis work is divided into six chapters. The first chapter gives an introduction to queue computing, explaining the research objectives and approach taken to develop the topic.
The second chapter develops a literature review of processor architecture. It gives detailed analysis of the Produced Order Queue Computing, the Circular Queue Register structure, and the Queue core in terms of architecture, ISA (Instruction Set Architecture), data path and control.
The third chapter discusses the specific features (like level order traversal, operands not explicitly specified, absence of register renaming, etc) which enable it extract high instruction level parallelism (ILP), lower power consumption and smaller code size. The RISC processor is also closely examined and analysed alongside the Queue processor.
Chapter four presents the methodology employed to carry out not just a theoretical analysis but simulations to support the higher performance of the Queue architecture over the RISC architecture.
The fifth chapter focuses on the results of the simulation and experiments carried out.
The final chapter summarizes and draws conclusions based on the work done. It further outlines future research areas with respect to the performance evaluation carried out.

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